DDR5 memory is just a few months away and we will start to see these new memory kits in the DIY PC market. The upcoming 12th Gen Intel CPU and 600 Series chipset, as well as AMD’s Zen4 architecture, are said to support and will make use of DDR5 memory. Kingston recently announced that they have sent its overclockable DDR5 modules to motherboard partners for qualifications and validation. Last month, we also get to see early DDR5 SODIMM and UDIMM from Crucial. So, in this article let’s take a quick look at some of the advantages of DDR5 memory vs the current DDR4.
Advantages of DDR5 vs DDR4
DDR5 is the next generation of DRAM that is expected to be used in the upcoming Intel and AMD platforms. DDR5 memory offers improved reliability, maintainability, and performance while reducing power consumption.
DDR4 memory speed is typically around 1600MHz to 3200MHz. Anything higher than 3200MHz is usually an “overclocked” memory module, like the DDR4-3600MHz and DDR4-4000MHz memory kits. DDR5 offers increased performance and bandwidth with speeds of 3200MHz up to 64000MHz of speed.
Not only does DDR5 offers faster performance, but consumes less power as well. DDR4 memory has a VDD / VDDQ / VPP of 1.2/1.2/2.5 respectively. Meanwhile, DDR5 memory only has 1.1/1.1/1.8. Not only that, DDR5 offers improved voltage margins and reduced BOM costs.
DDR5 can also accommodate higher densities. DDR4 typically supports around 2Gb to 16Gb, meanwhile, DDR5 can accommodate 8Gb to 64Gb. This means that not only will we see faster DDR5 memory, but higher capacities as well. Perhaps 32GB or 64GB would be the “new 8GB or 16GB” memory capacity when DDR5 is released.
DDR5 memory also supports on-die ECC, although I am not sure at this point if this feature will be supported on all DDR5 memory kits, regardless of the brand or model. You can check out the rest of the advantages of the DDR5 memory from the table below.
| Feature/Option | DDR5 | DDR4 | DDR5 Advantage |
|---|---|---|---|
| Data rates | 3200-6400 MT/s | 1600-3200 MT/s | Increases performance and bandwidth |
| V DD /V DDQ /V PP | 1.1/1.1/1.8 | 1.2/1.2/2.5 | Lowers power |
| Internal V REF | V REFDQ , V REFCA , V REFCS | V REFDQ | Improves voltage margins, reduces BOM costs |
| Device densities | 8Gb-64Gb | 2Gb-16Gb | Enables larger monolithic devices |
| Prefetch | 16n | 8n | Keeps the internal core clock low |
| DQ receiver equalization | DFE | CTLE | Improves opening of the received DQ data eyes inside the DRAM |
| Duty cycle adjustment (DCA) | DQS and DQ | None | Improves signaling on the transmitted DQ/DQS pins |
| Internal DQS delay monitoring | DQS interval oscillator | None | Increases robustness against environmental changes |
| On-die ECC | 128b+8b SEC, error check and scrub | None | Strengthens on-chip RAS |
| CRC | Read/Write | Write | Strengthens system RAS by protecting read data |
| Bank groups (BG)/banks | 8 BG x 2 banks (8Gb x4/x8) 4 BG x 2 banks (8Gb x16) 8 BG x 4 banks (16-64Gb x4/x8) 4 BG x 4 banks (16-64Gb x16) | 4 BG x 4 banks (x4/x8) 2 BG x 4 banks (x16) | Improves bandwidth/performance |
| Command/address interface | CA<13:0> | ODT, CKE, ACT, RAS, CAS, WE, A | Dramatically reduces the CA pin count |
| ODT | DQ, DQS, DM, CA bus | DQ, DQS, DM/DBI | Improves signal integrity, reduces BOM costs |
| Burst length | BL16, BL32 (and BC8 OTF, BL32 OTF) | BL8 (and BL4) | Allows 64B cache line fetch with only 1 DIMM subchannel. |
| MIR ("mirror" pin) | Yes | None | Improves DIMM signaling |
| Bus inversion | Command/address inversion (CAI) | Data bus inversion (DBI) | Reduces V DDQ noise on modules |
| CA training, CS training | CA training, CS training | None | Improves timing margin on CA and CS pins |
| Write leveling training modes | Improved | Yes | Compensates for unmatched DQ-DQS path |
| Read training patterns | Dedicated MRs for serial (userdefined), clock and LFSR -generated training patterns | Possible with the MPR | Makes read timing margin more robust |
| Mode registers | Up to 256 x 8 bits (LPDDR type read/write) | 7 x 17 bits | Provides room to expand |
| PRECHARGE commands | All bank, per bank, and same bank | All bank and per bank | PREsb enables precharging-specific bank in each BG |
| REFRESH commands | All bank and same bank | All bank | REFsb enables refreshing of specific bank in each BG |
| Loopback mode | Yes | None | Enables testing of the DQ and DQS signaling |
Source: Crucial TW
DDR5 vs DDR4 Price and Availability
While there are still several months before we see DDR5 memory kits become the norm; expect that early DDR5 memory kits would be more expensive than the current DDR4 kits. I can remember when DDR4 was first released, and it was around double the price of a DDR3 memory kit of the same capacity.
Expect to see DDR5 memory kits once Intel and AMD release their respective DDR5-capable platform. For Intel, we expect the 12th Gen Alder Lake CPUs will support DDR5 memory. And they are expected to be released towards the end of this year. Meanwhile, for AMD, its upcoming Zen4 architecture should be able to support DDR5 technology as well. For we won’t be seeing AMD’s next-gen until some time in 2022 (2nd half).
